is a comprehensive design constraints management solution of modern SoC design. As the complexity of SoC is increasing, a clock network is often made up of hundreds of clocks. Hence the validation of clock constraints is inevitable. The requirement of lower power consumption of SoC results in the implementation of various lower power design techniques with carefully validated design constraints.
Navis-CM offers the low power design constraints management, the clock design constraints management, and power state aware power estimation features.
- Area estimation
- Clock structure analysis
- Low power design intent analysis
- Analytic power estimation
- Visualization of the clock tree structure and clock design rule check
- Validation and edition of power constraints with graphical debugging environment
- Design constraints management in early design stage