RTL Hierarchical Floorplanning Solution

Navis-FP is power and timing aware RTL floorplanning tool. It also optimizes the number and location of power pads to meet target IR-drop and SSO noise margin in the early design stage with PadOptima option.

Navis-FP enables you to minimize the unnecessary design iterations and to achieve the time to market of your valuable SoC product. It is industry proven design planning solution and allows the design information sharing between the system design group and the physical layout implementation group.

Key Features

  • RTL design exploration

  • Hierarchical Floorplanning

  • Constraint driven RTL floorplanning
  • Efficient pin positioning
  • Bus performance analysis
  • Interconnect net delay estimation
  • Clock tree modeling
  • Routing congestion analysis
  • Bump array generation
  • With PadOptima optional
  • Optimal pad configuration
  • RDL routing feasibility analysis


  • Constraint driven RTL floorplanning and design exploration
  • Feasibility analysis of package design
  • Fast design iteration