Navis-FP

Early SoC Design Planning Solution

Navis-FP is power and timing aware design planning solution with RTL floorplanning. It also optimizes the number and location of power pads to meet target IR-drop and SSO noise margin in early design stage with PadOptima option.

It enables you to minimize the unnecessary design iterations and to achieve the time to market of your valuable SoC product. Navis-FP is industry proven design planning solution and it allows the design information sharing between the system design group and the physical layout implementation group.

Key Features

  • RTL design exploration

  • Constraint driven RTL floorplanning
  • Efficient pin positioning
  • Bus performance analysis
  • Interconnect net delay estimation
  • Clock tree modeling
  • Routing congestion analysis
  • Optional power network prototyping
  • Bump array generation
  • With PadOptima optional
  • Optimal pad configuration
  • RDL routing analysis

Benefits

  • Constraint driven RTL floorplanning and design exploration
  • Feasibility analysis of package design
  • Fast design iteration