Transistor Level Critical Path Analyzer

Product Concept

Transistor level circuit simulation is the essential step of the integrated circuit (IC) design. However, it is generally impractical to simulate the entire SoC at the transistor level. Designers need to identify the critical path and should be able to analyze the selected critical path with highest accuracy within the limited design time. TRASTA automatically identifies the critical path and enables designers to analyze the critical path with highest precision. TRASTA automatically identifies the unique devices of the design and generate the gate level circuit with topology marching and channel connected extraction techniques. The timing characteristics of extracted gate level cells are automatically characterized and it is used in Static Timing Analysis (STA) step. TRASTA provides a built-in STA engine and SPICE netlist generation capability with back-annotated parasitics.

Key Features

  • TR Level Critical Path Analisys
  • Pattern matching for sub-circuit identification
  • CCG cell characterization
  • Mixed level static timing analysis
  • Critical path analysis by TR level or CCG level
  • Spice netlist generation with annotated parasitic
  • 3rd party circuit simulator interface
  • Graphical visualization of analysis result
  • Fast interface with mixed signal waveform viewer
  • Interactive cross-probing with 3rd party tools


  • Efficient critical path tracing
  • Automatic critical path extraction
  • Fast critical path analysis
  • Unified environment for STA and dynamic simulation