Navis-Pro is a comprehensive RTL design planning solution including chip estimation, design constraints validation, and floorplanning. As the complexity of system on chip (SoC) design increases over hundreds of millions of gates and lower power consumption is required, the needs for the early stage design planning solution becomes critical. Navis-Pro is power and timing aware pre-RTL design planning solution which predicts and prevents the IC implementation problems. The design planning solution should validate and manage the power, area, and timing constraints through the entire design process. Navis-Pro consists of three components: Navis-ES, Navis-DI, and Navis-FP. The key features are specification based chip estimation, power and clock design rule check, and floorplanning respectively.