NavisPro is a comprehensive RTL design planning solution including chip estimation, design constraints validation, and floorplanning. As the complexity of system on chip (SoC) design increases over billion gate and lower power consumption is required, the needs for the early stage design planning solution becomes critical. NavisPro is power and timing aware RTL design planning solution which predicts and prevents the IC implementation problems. The design planning solution should validate and manage the power, area, and timing constraints through the entire design process. NavisPro consists of Navis-CM and Navis-FP. The key features RTL design exploration, design constraints management, and hierarchical floorplanning.