is an interactive design exploration and timing debugging tool in post-layout design stage. Timing closure is the painful task to find and fix the timing problems of hundreds of millions of gates design within the limited time because the task requires multiple iterations of Static Timing Analysis (STA) at the post-layout stage. Moreover, the process variation effect on timing should be considered to find and fix the timing violation of the design and this makes the task of timing closure harder to complete on schedule.
TimingInspector provides efficient and comprehensive physical aware timing ECO solution to cover all design constraints and corners with intuitive multi-way analysis features including timing path analysis, clock tree analysis, and I/O path analysis. In the timing debugging process, the timing violation of the primary I/O path and clock tree path should be fixed prior to the debugging of timing violation of the data paths. TimingInspector has unique design hierarchy management feature, it can trace the timing path through the sub hierarchy design blocks without design flattening. Designers can consider the real cell placement and signal routing of the design when they fix the timing violation manually.
- Efficient path based timing debugging in multiple design views
- Visualization of clock tree and skew distribution
- Automatic and manual clock skew optimization
- GUI based manual timing fix with incremental timing update
- Ease of use
- Intuitive timing debugging in multiple design views
- Quick identification of problems in clock and IO timing
- Fast what-if analysis of path timing using interactive design editing
- MMMC clock timing views and skew optimization
- Physical aware ECO with hierarchical design handling and path tracing