Pillar-DP®-SVP is a comprehensive pre-RTL silicon virtual prototyping (SVP) solution including micro architecture level power and area estimation, hierarchical floorplanning, package aware IO pad configuration, and automatic power network prototyping. In addition to the SVP capability, the chip level IP integration feature and the constraints interface feature to the integrated chip (IC) implementation help you achieve the first-silicon-success and the time-to-market.

Pillar-DP®-SVP Flow

The complexity of leading edge system-on-chip (SoC) designs is over one hundred millions of logic gates, and the requirement for the lower power consumption and higher performance makes it difficult to estimate the real design problems occurring in the IC implementation stage.

The conventional design methodology with synthesis and P&R (Placement and Routing) cannot afford to predict the development schedule because of the unexpected design iterations due to the IC implementation problems. So, we need proper electronic design automation (EDA) tools which allow the design information sharing between the system design group and the chip implementation group.
The solution is the ESL SVP tool allowing the successful RTL hand-off, and its required capabilities are intellectual property (IP) based chip level integration, micro architecture level power and area estimation, mixed level floorplanning, package aware IO pad configuration, and power network prototyping.