Entasys provides an industry proven design planning solution in early design stage and design debugging and verification solutions in post layout design stage. Mixed signal design analysis solution is another focus area.

Constraint driven RTL design planning:

The design planning solution consists of process technology aware analytic power estimator, I/O pad configuration optimizer, abstraction level independent floorplanner, and power network synthesizer. The main objective of the design planning solution is to enable SoC designers to achieve the first-time silicon success with minimum design turnaround time(TAT). By the elimination of the unnecessary design iterations with fast and accurate prediction and efficient prevention of the power and SI related design errors at earlier design stage, designers can meet the TAT requirement.

Mixed signal critical path analysis:

Transistor level full chip timing verification is very time consuming and painful task, and it is generally considered as impractical to simulate the entire SoC at the TR level. Entasys provides a solution which automatically identifies the critical path, builds the partial circuit with every required parasitics, and allows users to analyze the critical path with highest precision.

Clock skew optimization and Post-layout timing debugging:

Entasys provides an efficient and comprehensive physical aware timing debugging solution to cover all timing constraints and corners with intuitive multi-way analysis features including timing path analysis, clock tree analysis, and I/O path analysis.