Early SoC Design Planning Solution

Navis is power and timing aware pre-RTL design planning solution which predicts and prevents the IC implementation problems and optimizes the number and location of power pads to meet target IR-drop and SSO noise margin in early design stage. It enables you to minimize the unnecessary design iterations and to achieve the time to market of your valuable SoC product. Navis is industry proven design palnning solution and it allows the design information sharing between the system design group and the physical layout implementation group.


  • RTL design exploration
  • Power and area estimation
  • Optimal pad configuration
  • Initial floorplanning
  • Bus performance analysis
  • Interconnect net delay estimation
  • Clock tree modeling
  • Routing congestion analysis
  • Power network prototyping


  • Predict and prevent the IC implementation problems in pre-RTL design stage
  • Start with mixed level design data
  • Feasibility analysis of package design
  • Fast design iteration