PadLVS supplements the existing LVS verification flow by pad ring connectivity check and unwanted power/ground net connection check during the layout design stage. The lack of proper automatic CAD tools for I/O pad configuration and verification causes a human error in pad ring connectivity implementation frequently and it is very painful and time consuming task to fix the design violation. PadLVS eliminates the unnecessary layout design iterations with fast and accurate verification of the power net connectivity of I/O PADs.
Key Features and Benefits
- Exact PAD ring pattern extraction - Extracts the ring pattern of I/O pads from the LEF file and GDS-II file.
- Comparison of user power intention & layout design - PadLVS checks the consistency between power net specification and layout design.
- Electrical short check - PadLVS can verify the electrical short of routing pattern of power nets in layout design.
- Integration with any design verification environment without extra effort - Interfaces 3rd party layout design tools with standard formats like LEF, DEF and GDS-II.
- Efficient GUI environment