DesignAdvisor is a comprehensive design constraints management solution of modern SoC design. As the complexity of a SoC is increasing, a clock network is often made up of hundred of clocks and the validation of clock constraints is inevitable. The requirement of lower power consumption of SoC results in the implementation of various lower power design techniques with carefully validated design constraints. DesignAdvisor offers the logical design rule check of the design, low power design constraints management and the clock design constraints management features.
Key Features and Benefits
- Logical design rule check
- Analysis clock structure
- Power domain analysis
- Clock network analysis
- Trace clock tree from source to sink
- Check designer intent for low power design
- Verifies existing floating port, feedback loop, using don’t use cell, etc
- Visualize logical rule violation point by schematic or design netlist.
- Support cross-probing between schematic and design netlist
- Graphical debugging environment including source and schematic viewer
- Design statistics report