is a simple but accurate power and area estimation tool of system-on-a-chip (SOC) design in micro-architecture level. At the early stage of system-on-chip (SOC) design, many unknown design parameters make it difficult to estimate the power consumption and area of the chip accurately.
Navis-ES begins with specifying a system-level specification of a SOC design, which includes the information of process technology, number of IO pins with pad assignment, clock/power domains, and identification of the macro blocks such as hard/soft macros and memory. Most of this information is derived from previous project or defined in the design specification. Navis-ES estimates the power consumption with built-in analytic power estimator and estimate the area with interactive floorplanner.
- Interactive pre-RTL floorplanning
- Floorplan aware area estimation
- Scenario based peak power estimation
- Yield estimation
- Available bump count estimation
- Rapid what-if analysis
- Design comparison between different process technology adoptions
- Estimation report generation & viewer
- Floorplan aware power and area estimation
- Process aware peak power estimation
- Prediction and prevention of layout design problems with rapid what-if analysis
- Easy comparison of the variations caused by different process technology