is a comprehensive design constraints management solution of modern SoC design. As the complexity of a SoC is increasing, a clock network is often made up of hundreds of clocks. Hence the validation of clock constraints is inevitable. The requirement of lower power consumption of SoC results in the implementation of various lower power design techniques with carefully validated design constraints.
Navis-DI offers the logical design rule check of the design, low power design constraints management and the clock design constraints management features.
- Logical design rule check
- Clock structure analysis
- Low power design intent analysis
- Analytic power estimation
- Available bump count estimation
- Visualization of logical design rule violation and intuitive cross-probing between schematic and design netlist
- Visualization of the clock tree structure and clock design rule check
- Validation and edition of power constraints with graphical debugging environment
- Design constraints management in early design stage